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CDP1852/3, CDP1852C/3
High-Reliability Byte-Wide Input/Output Port
Description
The CDP1852/3 and CDP1852C/3 are parallel, 8-bit, modeprogrammable input/output ports. They are compatible and will interface directly with CDP1800-Series microprocessors. They are also useful as 8-bit address latches when used with the CDP1800 multiplexed address bus and as I/O ports in general-purpose applications. The mode control is used to program the device as an input port (mode = 0) or as an output port (mode = 1). The SR/SR output can be used as a signal to indicate when data is ready to be transferred. In the input mode, a peripheral device can strobe data into the CDP1852/3, and microprocessor can read that data by device selection. In the output mode, a microprocessor strobes data into the CDP1852/3, and handshaking is established with a peripheral device when the CDP1852/3 is deselected. In the input mode, data at the data-in terminals (DI0-DI7) is strobed into the port's 8-bit register by a high (1) level on the clock line. The negative high-to-low transition of the clock latches the data in the register and sets the service request output low (SR/SR = 0). When CS1/CS1 and CS2 are high (CS1/CS1 and CS2 = 1), the three-state output drivers are enabled and data in the 8-bit register appear at the data-out terminals (DO0-DO7). When either CS1/CS1 or CS2 goes low (CS1/CS1 or CS2 = 0), the data-out terminals are tristated and the service request output returns high (SR/SR =1). In the output mode, the output drivers are enabled at all times. Data at the data-in terminals (DI0-DI7) is strobed into the 8-bit register when CS1/CS1 is low (CS1/CS1 = 0) and CS2 and the clock are high (1), and are present at the dataout terminals (DO0-DO7). The negative high-to-low transition of the clock latches the data in the register. The SR/SR output goes high (SR/SR = 1) when the device is deselected (CS1/CS1 = 1 or CS2 = 0) and returns low (SR/SR = 0) on the following trailing edge of the clock. A CLEAR control is provided for resetting the port's register (DO0-DO7 = 0) and service request flip-flop (input mode: SR/SR = 1 and output mode: SR/SR = 0). The CDP1852/3 is functionally identical to the CDP1852C/3. The CDP1852/3 has a recommended operating voltage range of 4V to 10.5V, and the CDP1852C/3 has a recommended operating voltage range of 4V to 6.5V. The CDP1852/3 and CDP1852C/3 are supplied in 24-lead, dual-in-line side-brazed ceramic packages (D suffix).
March 1997
Features
* Static Silicon-Gate CMOS Circuitry * Parallel 8-Bit Data Register and Buffer * Handshaking Via Service Request Flip-Flop * Low Quiescent and Operating Power * Interfaces Directly with CDP1800-Series Microprocessors * Single Voltage Supply * Full Military Temperature Range (-55oC to +125oC)
Ordering Information
PACKAGE SBDIP TEMP. RANGE
o o
5V
10V
PKG. NO
-55 C to +125 C CDP1852CD3 CDP1852D3 D24.6
Pinout
CDP1852/3, CDP1852C/3 (SBDIP) TOP VIEW
CSI/CSI 1 MODE 2 DI0 3 DO0 4 DI1 5 DO1 6 DI2 7 DO2 8 DI3 9 DO3 10 CLOCK 11 VSS 12 24 VDD 23 SR/SR 22 DI7 21 DO7 20 DI6 19 DO6 18 DI5 17 DO5 16 DI4 15 DO4 14 CLEAR 13 CS2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1
File Number
1694.2
CDP1852/3, CDP1852C/3 Block Diagram of CDP1852/3
CSI/CSI CS2 1 13 DEVICE SELECT DECODE CONTROL LOGIC 23 SR/SR 24 12 VDD VSS
MODE 2 CLOCK 11 CLEAR 14 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 3 5 7 9 16 18 20 22 RESET CLOCK
ENABLE THREESTATE OUTPUT DRIVERS
8-BIT DATA REGISTER
4 6 8 10 15 17 19 21
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
POLARITY DEPENDS ON MODE MODE = 1 MODE = 0 P1 P23 CSI SR CSI SR
FIGURE 1.
CS2 13 CSI/CSI 1 S D VSS Q SERVICE REQUEST LATCH SR/SR 23
MODE 2 CLEAR 14
R CL
CLOCK 11
VDD DI0 3 P TG N P DO0 4 N P TG N
VSS
DI1 5
DO1 6
D17 22
DO7 21
FIGURE 2. CDP1852/3 LOGIC DIAGRAM
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CDP1852/3, CDP1852C/3
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD): (All Voltages Referenced to VSS Terminal) CDP1852/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +11V CDP1852C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
:
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . 65 20 Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering): At distance 1/16 1/32 in (1.59 0.79mm) From Case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
TA = Full-Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges. LIMITS CPP1852/3 PARAMETER DC Operating Voltage Range Input Voltage Range MIN 4 VSS VIN = 0 or VDD, Except as Noted LIMITS -55oC, +25oC PARAMETER Quiescent Device Current (Note 1) SYMBOL IDD TEST CONDITIONS VDD = 5V VDD = 10V Output Low Drive (Sink) Current IOL VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V Output High Drive (Source) Current IOH VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V Output Voltage Low Level VOL VDD = 5V, IOL = 0A VDD = 10V, IOL = 0A Output Voltage High Level VOH VDD = 5V, IOL = 0A VDD = 10V, IOL = 0A Input Low Voltage VIL VDD = 5V, VO = 0.2, 4.8V VDD = 10V, VO = 0.2, 9.8V Input High Voltage VIH VDD = 5V, VO = 0.2, 4.8V VDD = 10V, VO = 0.2, 9.8V Input Leakage Low IIL VDD = 5V, VIN = 0V VDD = 10V, VIN = 0V Input Leakage High IIH VDD = 5V, VIN = 5V VDD = 10V, VIN = 10V MIN 2.6 6.1 -1.8 -4.4 4.9 9.9 3.5 7 MAX 10 20 0.1 0.1 1.5 3 -1 -1 1 1 +125oC MIN 1.9 4.1 -1.3 -2.9 4.8 9.8 3.5 7 MAX 100 300 0.2 0.2 1.5 3 -5 -5 5 5 UNITS A A mA mA mA mA V V V V V V V V A A A A MAX 10.5 VDD CDP1852C/3 MIN 4 VSS MAX 6.5 VDD UNITS V V
Static Electrical Specifications
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CDP1852/3, CDP1852C/3
Static Electrical Specifications
VIN = 0 or VDD, Except as Noted (Continued) LIMITS -55oC, +25oC PARAMETER Three-State Output Leakage Low SYMBOL IOZL TEST CONDITIONS VDD = 5V, VO = 0V VDD = 10V, VO = 0V Three-State Output Leakage High IOZH VDD = 5V, VO = 5V VDD = 10V, VO = 10V Input Capacitance Output Capacitance CIN COUT Note 2 Note 2 MIN MAX -1 -1 1 1 10 15 +125oC MIN MAX -5 -5 5 5 10 15 UNITS A A A A pF pF
NOTES: 1. The CDP1852C/3 meets all 5V static electrical specifications of the CDP1852/3 except +125oC quiescent device current for which the limit is IDD = 300A. 2. Input and output capacitance are guaranteed but not tested.
Static Burn-In Circuit
VDD 1 VDD 2 3 4 5 6 7 8 9 10 11 12 VSS 24 23 22 21 20 19 18 17 16 15 14 13 VSS
TYPE NO. CDP1852/3 CDP1852C/3
VDD 11V 7V
TEMPERATURE +125oC +125oC
TIME 160 Hrs. Min. 160 Hrs. Min.
ALL RESISTORS 47k (20%)
Dynamic Electrical Specifications
Mode = 0 Input Port, See Figure 3, Input tr, tf 15ns; CL = 50pF LIMITS (NOTE 1) -55oC, +25oC MAX +125oC (NOTE 1) MIN 360 180 200 110 160 80 -10 -5 MAX UNITS ns ns ns ns ns ns ns ns
PARAMETER Select Duration
SYMBOL tSW
VDD VOLTS 5 10
(NOTE 1) MIN 250 150 150 90 110 50 -10 -5
Clock Pulse Width
tWW
5 10
Clear Pulse Width
tCLR
5 10
Data-In to Clock Fall Setup Time
tDS
5 10
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CDP1852/3, CDP1852C/3
Dynamic Electrical Specifications
Mode = 0 Input Port, See Figure 3, Input tr, tf 15ns; CL = 50pF (Continued) LIMITS (NOTE 1) -55oC, PARAMETER Data-In After Clock Fall Hold Time SYMBOL tDH VDD VOLTS 5 10 Propagation Delay Times: Clear to SR tRSR 5 10 Clock to SR tCSR 5 10 Deselect to SR tSSR 5 10 NOTE: 1. Time required by a device to allow for the indicated function.
(NOTE 1) CS1 * CS2 tWW tDH DATA IN tDS DATA BUS HIGH IMPEDANCE tSSR tRSR tCSR tSW
+25oC MAX 200 110 175 110 175 110
+125oC (NOTE 1) MIN 170 100 MAX 340 170 220 130 240 120 UNITS ns ns ns ns ns ns ns ns
(NOTE 1) MIN 150 70 -
CLOCK
SR
CLEAR
tCLR
NOTE: 1. CS1 * CS2 is the overlap of CS1 = 1 and CS2 = 1.
MODE = 0 TRUTH TABLE CLOCK X 0 0 1 NOTE: 1. CS1 * CS2 = CS1 = 1, CS2 = 1. CS1 * CS2 (Note 1) 0 1 1 1 CLEAR X 0 1 X DATA OUT EQUALS High Impedance 0 Data Latch Data In SR = 0 Clock =
SERVICE REQUEST TRUTH TABLE CS1 or CS2 = or CLEAR = 0
SR = 1
FIGURE 3. MODE = 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
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CDP1852/3, CDP1852C/3
Dynamic Electrical Specification
Mode = 1 Output Port, See Figure 4, Input tr, tf 15ns; CL = 50pF LIMITS (NOTE 1) -55 C, +25oC PARAMETER Clock Pulse Width SYMBOL tCLK VDD VOLTS 5 10 Write Width Duration tWW 5 10 Clear Pulse Width tCLR 5 10 Data-In to Clock Fall Setup Time tDS 5 10 Data Hold from Write Termination tDH 5 10 Select-After Clock-Fall Hold Time tSH 5 10 Propagation Delay Times: Clear to Data tRDO 5 10 Write to Data Out tWDO 5 10 Data In to Data Out tDDO 5 10 Clear to SR tRSR 5 10 Clock to SR tCSR 5 10 Deselect to SR tSSR 5 10 NOTE: 1. Time required by a device to allow for the indicated function. (NOTE 1) MIN 170 90 200 110 110 60 -10 -5 130 70 0 0 MAX 215 140 250 130 150 80 175 120 170 90 170 90
o
+125oC (NOTE 1) MIN 260 130 260 130 135 75 -10 -5 170 90 0 0 MAX 290 190 350 190 200 100 240 160 240 120 240 120 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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CDP1852/3, CDP1852C/3
(NOTE 2) tWW (NOTE 1) CS1 * CS2
tSH tDS tDH tCLK
CLOCK DATA IN
tDDO DATA OUT tRDO tWDO SR CLEAR tRSR tCLR tSSR tCSR
NOTES: 1. CS1 * CS2 is the overlap of the CS1 = 0 and CS2 = 1. 2. Write is the overlap of CS1 * CS2 and clock. MODE = 1 TRUTH TABLE CLOCK 0 0 X 1 NOTE: 1. CS1 * CS2 = CS1 = 0, CS2 = 1 FIGURE 4. MODE = 1 OUTPUT PORT TIMING WAVEFORMS AND TRUTH TABLES CS1 * CS2 (NOTE 1) X X 0 1 CLEAR 0 1 1 X 0 Data Latch Data Latch Data In DATA OUT EQUALS CS1 or CS2 SR = 1 SERVICE REQUEST TRUTH TABLE Clock * (CS1 * CS2) or CLEAR = 0 SR = 0
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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